Blogs
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Internal I/O subsystem- IBM Power E1050
The internal I/O subsystem of the Power E1050 server is connected to the PCIe Express…
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Active Memory Mirroring- IBM Power E1050
The Power E1050 server can mirror the Power Hypervisor code across multiple memory DDIMMs. If…
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Memory placement rules- IBM Power E1050
Each Power10 chip requires a minimum of two DDIMMs that are installed. Because each processor…
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Memory activations- IBM Power E1050
To use the physical memory, it must be activated. For that action, the Power E1050…
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Differential Dual Inline Memory Module- IBM Power E1050
The Power10 processor-based E1050 server introduces a new 4U tall DDIMM, which has a new…
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Comparing Power10, Power9, and Power8 processors- IBM Power E1050
The Power10 processor-based systems are using three different processor module packages: Ê SCMs, which are…
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Power and performance management- IBM Power E1050
Power10 processor-based servers implement an enhanced version of the power management EnergyScale technology. As in…
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SMP interconnect and accelerator interface- IBM Power E1050
The Power10 processor provides a highly optimized, 32-Gbps differential signaling technology interface that is structured…
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On-chip L3 cache and intelligent caching- IBM Power E1050
The Power10 processor includes a large on-chip L3 cache of up to 120 MB with…
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Processor module options- IBM Power E1050
The Power E1050 server uses DCMs. The server can be populated with either two, three,…