The Power10 processor-based systems are using three different processor module packages:
Ê SCMs, which are based on one Power10 chip
Ê DCMs, which combine two Power10 chips where both Power10 chips contribute active processor cores
Ê Entry single-chip modules (eSCMs), which combine two Power10 chips, but all active processor core resources are bundled on one of the two chips
Power E1050 servers use exclusively SCM modules with up to 15 active SMT8-capable cores. These SCM processor modules are structural and performance-optimized for usage in scale-up multi-socket systems.
DCM modules with up to 30 active SMT8 capable cores are used in 4-socket Power E1050 servers, and 2-socket Power S1022 and Power S1024 servers. eSCMs with up to eight active SMT8-capable cores are used in 1-socket Power S1014 and 2-socket Power S1022s servers. DCM and eSCM modules are designed to support scale-out 1- to 4-socket Power10 processor-based servers.
54 IBM Power E1050: Technical Overview and Introduction
Table 2-6 compares key features and characteristics of the Power10, Power9, and Power8 processor implementations as used in enterprise class scale-up and the Power10 processor-based scale-out servers.
Table 2-6 Comparison of the Power10 processor technology to prior processor generations
a. Best of class typical frequency range, where the lower limit of the range coincides with the maximum static or nominal frequency.
b. Static random-access memory.
c. Embedded dynamic random-access memory.
d. Power10 processor memory logic and the memory subsystem of Power10 processor-based servers can use DDR5 technology DIMMs.
e. Only DDR3 memory CDIMMs, which are transferred in the context of a model upgrade from Power E870, Power E870C, Power E880, or Power E880C servers to a Power E980 server, are supported.
Chapter 2. Architecture and technical overview 55
2.2 Memory subsystem
The Power E1050 server uses the new and innovative OMI. OMI is a technology-neutral memory interface. The Power E1050 server supports DDIMMs that are based on DDR4 technology, which are plugged into the OMI slots. A maximum of 64 OMI slots are available in a server with all four processor sockets populated, with which a maximum of 16 TB of memory can be installed in to the server. In the following sections, the details about OMI and DDIMMs are described in more detail.
2.2.1 Open Memory Interface
The OMI is driven by eight on-chip MCUs, and it is implemented in two separate physical building blocks that lie in opposite areas at the outer edge of the Power10 die. Each area supports 64 OMI lanes that are grouped in four OMI ports. One port in turn consists of two OMI links with eight lanes each, which operate in a latency-optimized manner with unprecedented bandwidth and scale at 32-Gbps speed.
One Power10 processor chip supports the following functional elements to access main memory:
Ê Eight MCUs
Ê Eight OMI ports that are controlled one-to-one through a dedicated MCU
Ê Two OMI links per OMI port, for a total of 16 OMI links
Ê Eight lanes per OMI link for a total of 128 lanes, all running at 32-Gbps speed
The Power10 processor provides natively an aggregated maximum theoretical full-duplex memory interface bandwidth of 1 TBps per chip.
Memory interface architecture for dual-chip modules
The DCM that is used in the Power E1050 server combines two Power10 processor chips in one processor package. A total of 2 x 8 = 16 OMI ports and 2 x 16 = 32 OMI links are physically present on a Power10 DCM. But because the chips on the DCM are tightly integrated and the aggregated memory bandwidth of 8 OMI ports already culminates at a maximum theoretical full-duplex bandwidth of 1 TBps, only half of the OMI ports are active. Each chip of the DCM contributes four OMI ports and eight OMI links to facilitate main memory access. Figure 2-1 on page 35 and Figure 2-11 on page 61 show details about the OMI port designation and the physical location of the active OMI units of a DCM.
In summary, one DCM supports the following functional elements to access main memory:
Ê Four active MCUs per chip, for a total of eight MCUs per module.
Ê Each MCU maps one-to-one to an OMI port.
Ê Four OMI ports per chip, for at total of eight OMI ports per module.
Ê Two OMI links per OMI port for a total of eight OMI links per chip and 16 OMI links per module.
Ê Eight lanes per OMI link for a total of 128 lanes per module, all running at 32-Gbps speed.
The Power10 DCM provides an aggregated maximum theoretical full-duplex memory interface bandwidth of 512 GBps per chip and 1 TBps per module.
56 IBM Power E1050: Technical Overview and Introduction